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Cache memory
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#	Item
921	IMPROVING GATEWAY PERFORMANCE WITH A ROUTING-TABLE CACHE David C. Feldmeier Massachusetts Instituteof Technology Laboratory for computer Science Cambridge, Ma 02139 Add to Reading List Source URL: groups.csail.mit.edu Language: English - Date: 2010-02-19 12:48:15 Computer memory Associative arrays Central processing unit Cache algorithms CPU cache Internet Protocol Hop Hash table Lookup table Computing Computer networking Cache
922	On the Verification of Memory Management Mechanisms Iakov Dalinger∗ Mark Hillebrand∗ Add to Reading List Source URL: www.verisoft.de Language: English - Date: 2013-04-11 05:48:57 Central processing unit Computer memory Computing Memory management Memory management unit CPU cache Memory address Page table Interrupt Computer architecture Virtual memory Computer hardware
923	Notebook specifications[removed]HP Zbook 15 • OS: Windows 8.1 Enterprise 64 bit • CPU: Intel Core i7-4700MQ Quad Core (2,4 GHz, 6Mb Cache, Turbo 3,4GHz) • RAM: 8 GB (2x 4GB) 1600Mhz DDR3 memory (2 free slots) Add to Reading List Source URL: w3.tue.nl Language: English - Date: 2014-06-18 04:15:43 Apple Inc. Netbooks MacBook Air Dell Latitude Computer hardware Universal Serial Bus Computing
924	DataStax Enterprise 4.0 In-Memory Option A look at performance, use cases, and anti-patterns White Paper Table of Contents Add to Reading List Source URL: www.datastax.com Language: English - Date: 2014-02-26 13:46:30 Computing Central processing unit Database management systems Solid-state drive CPU cache Cache Page cache In-memory database Random-access memory Computer memory Computer hardware Memory management
925	A Better Reduction Theorem for Store Buffers Ernie Cohen1 and Norbert Schirmer2,? 1 arXiv:0909.4637v1 [cs.LO] 25 Sep 2009 Add to Reading List Source URL: arxiv.org Language: English - Date: 2009-09-25 04:48:39 Memory barrier Circular buffer Volatile variable CPU cache Cache Data buffer Page table Non-volatile memory Parallel computing Computer memory Computing Computer hardware
926	Locality-Aware Data Replication in the Last-Level Cache George Kurian, Srinivas Devadas Massachusetts Institute of Technology Cambridge, MA USA {gkurian, devadas}@csail.mit.edu Abstract Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-01-23 18:46:58 Computer memory CPU cache Central processing unit Cache algorithms MESI protocol Computer architecture Cache Computer hardware Computing
927	Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs Christopher W. Fletcher†∗, Ling Ren† , Xiangyao Yu† , Marten Van Dijk‡ , Omer Khan‡ , Srinivas D Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2014-01-23 18:47:27 CPU cache Dynamic random-access memory Synchronous dynamic random-access memory Side channel attack Microarchitecture DIMM CAS latency Static random-access memory SDRAM latency Computer memory Computer hardware Computing
928	A Secure Processor Architecture for Encrypted Computation on Untrusted Programs Christopher Fletcher Marten van Dijk Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2012-10-19 22:35:51 Computer engineering Computer memory Cache CPU cache Microprocessors Microarchitecture Computer hardware Central processing unit Computer architecture
929	Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia Lebedev, Srinivas Devadas Massachusetts Institute of Technology, Cambridge, Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-08-26 16:12:52 Parallel computing Computer memory Central processing unit Computer architecture Microprocessors CPU cache Multi-core processor Cache Memory coherence Computing Concurrent computing Computer hardware
930	The Locality-Aware Adaptive Cache Coherence Protocol George Kurian Omer Khan Srinivas Devadas Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-04-22 20:43:35 Computer memory Central processing unit CPU cache Computer architecture MESI protocol Acumem SlowSpotter Bus sniffing Cache Computer hardware Computing

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